Line data Source code
1 : /******************************************************************************
2 : * ETSI TS 103 634 V1.6.1 *
3 : * Low Complexity Communication Codec Plus (LC3plus) *
4 : * *
5 : * Copyright licence is solely granted through ETSI Intellectual Property *
6 : * Rights Policy, 3rd April 2019. No patent licence is granted by implication, *
7 : * estoppel or otherwise. *
8 : ******************************************************************************/
9 :
10 : #include "options.h"
11 : #include "wmc_auto.h"
12 : #include "functions.h"
13 :
14 : static const LC3_INT32 gainMSBbits[4] = {1, 1, 2, 2};
15 :
16 : static void read_bit_fl(LC3_UINT8* ptr, LC3_INT* mask_side, LC3_INT* bp_side, LC3_INT* bit);
17 : static void read_uint_fl(LC3_INT nbits, LC3_UINT8* ptr, LC3_INT* mask_side, LC3_INT* bp_side, LC3_INT* val);
18 :
19 : #ifdef CR9_C_ADD_1p25MS_LRSNS
20 : void readSNSData_fl(LC3_UINT8* ptr, LC3_INT32* bfi, LC3_INT32* mask_side_local, LC3_INT32* bp_side_local, const LC3_INT32* ltpf_idx_2_lrsns, LC3_INT32* sns_vq_idx, LC3PLUS_FrameDuration frame_dms, LC3_INT32 plc_trigger_SNS1, LC3_INT32 plc_trigger_SNS2);
21 : #else
22 : void readSNSData_fl(LC3_UINT8* ptr, LC3_INT32* bfi, LC3_INT32* mask_side_local, LC3_INT32* bp_side_local, LC3_INT32* sns_vq_idx, LC3PLUS_FrameDuration frame_dms, LC3_INT32* plc_trigger_SNS1, LC3_INT32* plc_trigger_SNS2);
23 : #endif
24 :
25 :
26 :
27 : #ifdef NEW_SIGNALLING_SCHEME_1p25
28 : void readLtpData_fl(LC3_UINT8* ptr, LC3_INT32* bfiPtr, LC3_INT32* mask_side, LC3_INT32* bp_side, LC3_INT32* ltpf_idx, LC3_INT32* rx_status, LC3_INT32* ltpfinfo_frame_cntr, LC3_INT16* mem_continuation);
29 : #endif
30 :
31 48076234 : void read_bit_fl(LC3_UINT8* ptr, LC3_INT* mask_side, LC3_INT* bp_side, LC3_INT* bit)
32 : {
33 48076234 : if (ptr[*bp_side] & *mask_side) {
34 22723346 : *bit = 1;
35 : } else {
36 25352888 : *bit = 0;
37 : }
38 :
39 48076234 : if (*mask_side == 128) {
40 5709827 : *mask_side = 1;
41 5709827 : *bp_side = *bp_side - 1;
42 : } else {
43 42366407 : *mask_side = *mask_side * 2;
44 : }
45 48076234 : }
46 :
47 6395801 : void read_uint_fl(LC3_INT nbits, LC3_UINT8* ptr, LC3_INT* mask_side, LC3_INT* bp_side, LC3_INT* val)
48 : {
49 : LC3_INT bit, i;
50 :
51 6395801 : read_bit_fl(ptr, mask_side, bp_side, val);
52 :
53 44044955 : for (i = 1; i < nbits; i++) {
54 37649154 : read_bit_fl(ptr, mask_side, bp_side, &bit);
55 37649154 : *val = *val + (bit << i);
56 : }
57 6395801 : }
58 :
59 : #ifdef ENABLE_PADDING
60 590506 : LC3_INT paddingDec_fl(LC3_UINT8* bytes, LC3_INT nbbits, LC3_INT L_spec, LC3_INT bw_cutoff_bits, LC3_INT ep_enabled, LC3_INT* total_padding, LC3_INT *np_zero)
61 : {
62 : LC3_INT lastnz_threshold;
63 : LC3_INT val, padding_len_bits, padding_len;
64 : LC3_INT bp_side;
65 : LC3_INT mask_side;
66 590506 : LC3_UINT8* ptr = bytes;
67 :
68 590506 : LC3_INT nbbytes = nbbits >> 3;
69 : LC3_INT lastnz;
70 : LC3_INT bw_cutoff_idx;
71 590506 : LC3_INT nbits = getLastNzBits (L_spec);
72 :
73 590506 : if (nbits > nbbits)
74 : {
75 0 : return 1;
76 : }
77 :
78 590506 : *np_zero = 0;
79 :
80 590506 : *total_padding = 0;
81 :
82 590506 : bp_side = (nbbits - 1) >> 3;
83 590506 : mask_side = 1 << (8 - (nbbits - (bp_side << 3)));
84 :
85 590506 : if (bp_side < 19 || bp_side >= LC3PLUS_MAX_BYTES) {
86 0 : return 1;
87 : }
88 :
89 590506 : ptr = bytes;
90 :
91 590506 : if (bw_cutoff_bits > 0) {
92 590506 : read_uint_fl(bw_cutoff_bits, ptr, &mask_side, &bp_side, &bw_cutoff_idx);
93 : }
94 :
95 590506 : read_uint_fl(nbits, ptr, &mask_side, &bp_side, &lastnz);
96 :
97 590506 : lastnz_threshold = (1 << nbits) - 1 - 1;
98 :
99 590506 : while (lastnz == lastnz_threshold) {
100 0 : padding_len_bits = 16 - nbits - bw_cutoff_bits - 4;
101 :
102 : /*Read padding length*/
103 0 : read_uint_fl(padding_len_bits, ptr, &mask_side, &bp_side, &padding_len);
104 :
105 : /* Read 4 reserved bits */
106 0 : read_uint_fl(4, ptr, &mask_side, &bp_side, &val);
107 :
108 0 : if (ep_enabled == 0)
109 : {
110 : /* Discard padding length bytes */
111 0 : bp_side = bp_side - padding_len;
112 0 : *total_padding = *total_padding + padding_len + 2;
113 : }
114 : else
115 : {
116 0 : *total_padding = *total_padding + 2;
117 0 : *np_zero = *np_zero + padding_len;
118 : }
119 :
120 : /* check if minimum payload size is reached */
121 0 : if ((nbbytes - (*total_padding + *np_zero)) < 20) {
122 0 : return 1;
123 : }
124 :
125 : /* Read bandwidth bits */
126 0 : if (bw_cutoff_bits > 0) {
127 0 : read_uint_fl(bw_cutoff_bits, ptr, &mask_side, &bp_side, &bw_cutoff_idx);
128 : }
129 :
130 0 : read_uint_fl(nbits, ptr, &mask_side, &bp_side, &lastnz);
131 : }
132 :
133 590506 : if (ep_enabled != 0)
134 : {
135 0 : *total_padding = *total_padding + *np_zero;
136 : }
137 :
138 590506 : return 0;
139 : }
140 : #endif
141 :
142 :
143 : #ifdef NEW_SIGNALLING_SCHEME_1p25
144 0 : void readLtpData_fl(
145 : LC3_UINT8* ptr,
146 : LC3_INT32* bfiPtr,
147 : LC3_INT32* mask_side,
148 : LC3_INT32* bp_side,
149 : LC3_INT32* ltpf_idx,
150 : LC3_INT32* rx_status,
151 : LC3_INT32* ltpfinfo_frame_cntr,
152 : LC3_INT16* mem_continuation
153 : )
154 : {
155 0 : LC3_INT32 rx_current_status = -1;
156 : LC3_INT32 tmp, MSBs, LSBs;
157 :
158 : /* Hdr, information , bits used
159 : 00 , no lag info , no phase info sum=2
160 : 010, PhaseA,LTPF=0, lagAbits=4 , sum=7 : PLC may be activated, 4 MSbs
161 : 011, PhaseB,LTPF=0, lagBbits=4*, sum=7* : PLC may be activated, 4* = reduced lag resolution in Q_ltpf_Idx domain for PLC-activation
162 : 10 , PhaseA,LTPF=1, lagAbits=4 , sum=6 : LTPF activated
163 : 11 , PhaseB,LTPF=1, lagBbits=5 , sum=7 : LTPF activated
164 : */
165 :
166 0 : ltpf_idx[2] = -1; /* no ready lag available, conditionally decoded if phase is B, and consecutive A/B has arrived */
167 :
168 0 : read_uint_fl(2, ptr, mask_side, bp_side, &tmp);
169 0 : if (tmp == 0) /* "00" */
170 : {
171 0 : ltpf_idx[0] = 0; /* ltp ltpf/lag was not transmitted */
172 0 : ltpf_idx[1] = 0; /* ltpf activation bit zeroed */
173 :
174 0 : rx_status[0] = -32768; /* set unknown phase A , due to rx LTP==0 */
175 0 : rx_status[1] = -1; /* set unknown phase A MSBs content */
176 0 : *ltpfinfo_frame_cntr = -32768;
177 0 : assert(ltpf_idx[2] < 0); /* ltpf_idx[2] = -1; , no ready lag available */
178 : #ifdef FIX_LTPF_1p25
179 0 : *mem_continuation = 0; /* also kill lag continuation state */
180 : #endif
181 : }
182 0 : else if (tmp == 1) /* "01" */
183 : {
184 0 : ltpf_idx[0] = 1;
185 0 : ltpf_idx[1] = 0; /* LTP=1, LTPF=0, inactive ltpf */
186 0 : read_bit_fl(ptr, mask_side, bp_side, &rx_current_status);
187 :
188 0 : if (rx_current_status == 0)
189 : {
190 0 : rx_status[0] = 0; /* phaseA */
191 0 : read_uint_fl(4, ptr, mask_side, bp_side, &(rx_status[1])); /* read four MSBs, and store in rx_status[1] */
192 : #ifdef FIX_LTPF_1p25
193 0 : if (*mem_continuation == 0)
194 : {
195 0 : *mem_continuation = 1;
196 : }
197 : #endif
198 0 : *ltpfinfo_frame_cntr = 0; /*same as rx_status [0] */
199 : }
200 : else
201 : { /* LSB part of delta coded lag information */
202 0 : assert(rx_current_status == 1);
203 0 : read_uint_fl(4, ptr, mask_side, bp_side, &LSBs);
204 0 : LSBs = (LSBs << 1); /* NB Least Signifcant bit is on purpose always zero, truncation on encoder side */
205 0 : if ( rx_status[1] < 0 )
206 : {
207 0 : *bfiPtr = 1;
208 0 : return;
209 : }
210 0 : ltpf_idx[2] = ((rx_status[1] << 5) | LSBs); /* bitwise OR */
211 :
212 : /* check frame cntr info to not combine oldA with a newB */
213 0 : if (*ltpfinfo_frame_cntr != 1)
214 : {
215 0 : rx_status[0] = -32768; /*even number of bfi frames may have happened */
216 0 : ltpf_idx[1] = 0;
217 0 : ltpf_idx[2] = -1; /* send signal of non-decoded lag to PLC and LTPF decoder */
218 : }
219 : #ifdef FIX_LTPF_MEM_CONTINUATION
220 : else
221 : {
222 0 : *mem_continuation = 0;
223 : }
224 : # endif
225 0 : rx_status[0] = -32768;
226 0 : *ltpfinfo_frame_cntr = -32678;
227 : }
228 : }
229 : else
230 : { /* 2 or 3 */
231 0 : ltpf_idx[0] = 1;
232 0 : ltpf_idx[1] = 1; /* active ltpf */
233 :
234 0 : if (tmp == 2) /* 2="10" */
235 : {
236 : /* phaseA */
237 0 : read_uint_fl(4, ptr, mask_side, bp_side, &MSBs);
238 :
239 0 : rx_status[0] = 0;
240 0 : rx_status[1] = MSBs; /* remember the four MSBs */
241 : #ifdef FIX_LTPF_1p25
242 0 : if (*mem_continuation == 0)
243 : {
244 0 : *mem_continuation = 1;
245 : }
246 : #endif
247 0 : *ltpfinfo_frame_cntr = 0;
248 0 : assert(ltpf_idx[2] < 0); /* ltpf_idx[2] = -1; , no ready lag available */
249 : }
250 : else
251 : { /* 3="11" */
252 0 : assert(tmp == 3); /* phaseB */
253 0 : read_uint_fl(5, ptr, mask_side, bp_side, &LSBs); /* all 5 LSBs available*/
254 0 : if ( rx_status[1] < 0 )
255 : {
256 0 : *bfiPtr = 1;
257 0 : return;
258 : }
259 0 : ltpf_idx[2] = ((rx_status[1] << 5) | LSBs); /* bitwise OR */
260 :
261 : /* check frame cntr info to not combine oldA with a newB */
262 0 : if (*ltpfinfo_frame_cntr != 1)
263 : {
264 0 : ltpf_idx[1] = 0; /* turn off LTPF activation for now, so that ltpf_idx[2] is not read */
265 0 : ltpf_idx[2] = -1; /* send signal to PLC and ltpf_decoder, that phase B could not be decoded */
266 : }
267 0 : *ltpfinfo_frame_cntr = -32678; /*cntr init in phaseA*/
268 0 : rx_status[0] = -32768; /* phase init in phaseA*/
269 :
270 : #ifdef FIX_LTPF_MEM_CONTINUATION
271 0 : *mem_continuation = 0;
272 : #endif
273 : }
274 : }
275 :
276 : }
277 : #endif
278 :
279 :
280 : #ifdef CR9_C_ADD_1p25MS_LRSNS
281 590506 : void readSNSData_fl(LC3_UINT8* ptr, LC3_INT32* bfi, LC3_INT32* mask_side_local, LC3_INT32* bp_side_local, const LC3_INT32* ltpf_idx_2_lrsns,
282 : LC3_INT32* sns_vq_idx, LC3PLUS_FrameDuration frame_dms,
283 : LC3_INT32 plc_trigger_SNS1, LC3_INT32 plc_trigger_SNS2)
284 : #else
285 : void readSNSData_fl(LC3_UINT8* ptr, LC3_INT32* bfi, LC3_INT32* mask_side_local, LC3_INT32* bp_side_local, LC3_INT32* sns_vq_idx,
286 : LC3PLUS_FrameDuration frame_dms, LC3_INT32* plc_trigger_SNS1, LC3_INT32* plc_trigger_SNS2)
287 : #endif
288 : {
289 : LC3_INT32 tmp, submodeMSB, idxBorGainLSB, submodeLSB;
290 : #ifndef CR9_C_ADD_1p25MS
291 : (void) frame_dms;
292 : #endif
293 : #ifdef CR9_C_ADD_1p25MS_LRSNS
294 : LC3_INT32 read_legacy_sns_vq_bits;
295 : #endif
296 :
297 :
298 : UNUSED(frame_dms);
299 :
300 : #ifdef CR9_C_ADD_1p25MS_LRSNS
301 590506 : read_legacy_sns_vq_bits = 1;
302 590506 : if (frame_dms == LC3PLUS_FRAME_DURATION_1p25MS)
303 : {
304 0 : read_legacy_sns_vq_bits = 0; /* decode 9, 10, or 29/30 bits */
305 : }
306 :
307 590506 : if (read_legacy_sns_vq_bits != 0)
308 : {
309 : #endif
310 : /* SNS-VQ 1st stage */
311 590506 : read_uint_fl(5, ptr, mask_side_local, bp_side_local, &sns_vq_idx[SNS_IDX_LF]);
312 590506 : read_uint_fl(5, ptr, mask_side_local, bp_side_local, &sns_vq_idx[SNS_IDX_HF]);
313 :
314 : /* SNS-VQ 2nd stage side-info (3-4 bits) */
315 590506 : read_bit_fl(ptr, mask_side_local, bp_side_local, &submodeMSB);
316 :
317 590506 : read_uint_fl(gainMSBbits[submodeMSB * 2], ptr, mask_side_local, bp_side_local, &sns_vq_idx[SNS_IDX_GAIN]);
318 590506 : read_bit_fl(ptr, mask_side_local, bp_side_local, &sns_vq_idx[SNS_IDX_LS_INDA]);
319 :
320 : /* SNS-VQ 2nd stage VQ decoding (24-25 bits) */
321 590506 : if (submodeMSB == 0)
322 : {
323 285507 : read_uint_fl(25, ptr, mask_side_local, bp_side_local, &tmp);
324 285507 : if (tmp >= 33460056)
325 : {
326 : #ifdef CR9_C_ADD_1p25MS_LRSNS
327 0 : *bfi = plc_trigger_SNS1;
328 : #else
329 : *bfi = *plc_trigger_SNS1;
330 : #endif
331 0 : if (*bfi)
332 : {
333 0 : return;
334 : }
335 : }
336 285507 : idxBorGainLSB = floor(tmp / 2390004);
337 285507 : sns_vq_idx[SNS_IDX_A] = tmp - idxBorGainLSB * 2390004;
338 :
339 285507 : if (idxBorGainLSB < 2)
340 : {
341 15822 : submodeLSB = 1;
342 15822 : sns_vq_idx[SNS_IDX_GAIN] = sns_vq_idx[SNS_IDX_GAIN] * 2 + idxBorGainLSB;
343 15822 : sns_vq_idx[SNS_IDX_BORGAINLSB] = -2;
344 : }
345 : else
346 : {
347 269685 : submodeLSB = 0;
348 269685 : sns_vq_idx[SNS_IDX_BORGAINLSB] = idxBorGainLSB - 2;
349 : }
350 : }
351 : else
352 : {
353 304999 : read_uint_fl(24, ptr, mask_side_local, bp_side_local, &tmp);
354 304999 : if (tmp >= 16708096)
355 : {
356 : #ifdef CR9_C_ADD_1p25MS_LRSNS
357 0 : *bfi = plc_trigger_SNS2;
358 : #else
359 : *bfi = *plc_trigger_SNS2;
360 : #endif
361 0 : if (*bfi)
362 : {
363 0 : return;
364 : }
365 : }
366 :
367 304999 : if (tmp >= 15158272)
368 : {
369 11275 : submodeLSB = 1;
370 11275 : tmp -= 15158272;
371 11275 : sns_vq_idx[SNS_IDX_GAIN] = sns_vq_idx[SNS_IDX_GAIN] * 2 + (tmp & 1);
372 11275 : sns_vq_idx[SNS_IDX_A] = floor(tmp / 2);
373 11275 : sns_vq_idx[SNS_IDX_BORGAINLSB] = -2;
374 : }
375 : else
376 : {
377 293724 : submodeLSB = 0;
378 293724 : sns_vq_idx[SNS_IDX_A] = tmp;
379 293724 : sns_vq_idx[SNS_IDX_BORGAINLSB] = -1;
380 : }
381 : }
382 :
383 590506 : sns_vq_idx[SNS_IDX_SHAPEJ] = submodeMSB * 2 + submodeLSB;
384 :
385 : #ifdef CR9_C_ADD_1p25MS_LRSNS
386 : }
387 :
388 590506 : if (read_legacy_sns_vq_bits == 0)
389 : {
390 0 : LC3_INT32 shape_idx = -1;
391 0 : LC3_INT32 gain_idx = -1;
392 0 : LC3_INT32 aux_idx = -1;
393 0 : LC3_INT32 tmp_shape = -1;
394 0 : LC3_INT32 stop_bit = -1;
395 : /* SNS-VQ 1st stage in 9-10 bits */
396 0 : read_uint_fl(9, ptr, mask_side_local, bp_side_local, &sns_vq_idx[SNS_IDX_LF]);
397 0 : if (sns_vq_idx[SNS_IDX_LF] >= 510) /* stage 1A */
398 : {
399 0 : assert(sns_vq_idx[SNS_IDX_LF] < 512);
400 0 : sns_vq_idx[SNS_IDX_LF] -= 510; /* send only idx 0,1 */
401 0 : sns_vq_idx[SNS_IDX_HF] = -32768; /* unused */
402 0 : shape_idx = -9;
403 0 : sns_vq_idx[2] = shape_idx; /* actual signal to LR SNS vector reconstruction */
404 : }
405 : else
406 : {
407 : /* read stop bit */
408 0 : read_uint_fl(1, ptr, mask_side_local, bp_side_local, &stop_bit);
409 0 : sns_vq_idx[SNS_IDX_HF] = -32768; /* unused */
410 :
411 0 : if (sns_vq_idx[SNS_IDX_LF] < (2 * 170) && stop_bit != 0)
412 : {
413 : /*B or C , keep values 0...339 in sns_vq_idx[0] , so that stage1 B vs stage1 C can be determined later in the DecLR function */
414 0 : sns_vq_idx[2] = -10;
415 0 : sns_vq_idx[3] = ltpf_idx_2_lrsns[0]; /* forward LTP active flag */
416 0 : sns_vq_idx[4] = ltpf_idx_2_lrsns[1]; /* forward LTPF active flag */
417 : }
418 : else
419 : { /* stage1B + stage2 */
420 : /*0...169 in sns_vq_idx[0]*/
421 0 : if (sns_vq_idx[SNS_IDX_LF] < (2 * 170) && stop_bit == 0)
422 : {
423 0 : aux_idx = 0;
424 0 : if (sns_vq_idx[SNS_IDX_LF] >= (170))
425 : {
426 0 : aux_idx = 1;
427 0 : sns_vq_idx[SNS_IDX_LF] -= 170;
428 : }
429 0 : sns_vq_idx[SNS_IDX_HF] = aux_idx; /* aux bit for , LR_Split_LF, 29 bits */
430 :
431 0 : shape_idx = 0; /* point to splitLF parsing */
432 0 : sns_vq_idx[2] = shape_idx;
433 :
434 0 : read_uint_fl(2, ptr, mask_side_local, bp_side_local, &gain_idx);
435 0 : sns_vq_idx[3] = gain_idx;
436 :
437 : /* stage2 shape demux for LR_splitLF */
438 0 : read_uint_fl(10, ptr, mask_side_local, bp_side_local, &sns_vq_idx[4]); /* 10bits mPVQ(N=5,K=6) */
439 :
440 0 : if (sns_vq_idx[4] >= (SNSLR_NPVQ_L5K6 >> 1) + (1 << 5)) /* some limited bit error detection possible here */
441 : {
442 0 : *bfi = plc_trigger_SNS1;
443 0 : if (*bfi != 0)
444 : {
445 0 : return;
446 : }
447 : }
448 :
449 : /* determine section of splitLF mpvq(5,6)+P(8,2)+P(2,0) or mpvq(5,8)+P(10,0) */
450 0 : if (sns_vq_idx[4] < (SNSLR_NPVQ_L5K6 >> 1))
451 : {
452 0 : read_uint_fl(1, ptr, mask_side_local, bp_side_local, &tmp_shape); /* LS (8,2) */
453 0 : read_uint_fl(6, ptr, mask_side_local, bp_side_local, &sns_vq_idx[5]); /* mPVQ(8,2) */
454 0 : sns_vq_idx[5] = (sns_vq_idx[5] << 1) + tmp_shape; /* P(8,2) LS put as lsb */
455 : }
456 : else
457 : {
458 0 : sns_vq_idx[4] = sns_vq_idx[4] - (SNSLR_NPVQ_L5K6 >> 1); /* 5 LSBs of mpvq (5,8) */
459 :
460 0 : read_uint_fl(7, ptr, mask_side_local, bp_side_local, &sns_vq_idx[5]); /* 7 msbs of mPVQ(5,8) */
461 0 : sns_vq_idx[4] = (sns_vq_idx[5] << 5) | sns_vq_idx[4]; /* merge MSB's and LSBs */
462 0 : sns_vq_idx[5] = -8; /* signal to sns_decoder split_LF subshape to decode 8 lf pulses, and no hf pulses */
463 :
464 0 : if (sns_vq_idx[4] >= (SNSLR_NPVQ_L5K8 >> 1)) {
465 0 : *bfi = plc_trigger_SNS1;
466 0 : if (*bfi != 0) {
467 0 : return;
468 : }
469 : }
470 : }
471 : }
472 0 : else if (sns_vq_idx[SNS_IDX_LF] >= (2 * 170))
473 : {
474 0 : aux_idx = stop_bit;
475 0 : sns_vq_idx[SNS_IDX_LF] -= (2 * 170);
476 0 : sns_vq_idx[1] = aux_idx;
477 :
478 0 : shape_idx = 1; /* point to full parsing */
479 0 : sns_vq_idx[2] = shape_idx; /* LR_full , 30 bits */
480 :
481 0 : read_uint_fl(3, ptr, mask_side_local, bp_side_local, &gain_idx);
482 0 : sns_vq_idx[3] = gain_idx;
483 :
484 : /* stage2 shape demux for LR_full */
485 0 : read_uint_fl(17, ptr, mask_side_local, bp_side_local, &sns_vq_idx[4]); /* 16.666 bits mPVQ(N=15,K=5) */
486 :
487 0 : if (sns_vq_idx[4] >= (SNSLR_NPVQ_L15K5 >> 1))
488 : { /* fixenv shapes demultiplexing */
489 0 : sns_vq_idx[5] = (sns_vq_idx[4] - (SNSLR_NPVQ_L15K5 >> 1));
490 0 : if (sns_vq_idx[5] < (3 * (1 << 13)))
491 : { /*fix_env's "0,1,2" with 2 shiftbits and 11 remaining sign bits s1..s11 */
492 0 : sns_vq_idx[4] = 0;
493 0 : while (sns_vq_idx[5] >= (1 << 13)) {
494 0 : sns_vq_idx[5] = sns_vq_idx[5] - (1 << 13);
495 0 : sns_vq_idx[4] += 1;
496 : }
497 0 : assert(sns_vq_idx[4] >= 0 && sns_vq_idx[4] <= 3);
498 0 : assert(sns_vq_idx[5] >= 0 && sns_vq_idx[5] < (1 << 13));
499 : }
500 0 : else if (sns_vq_idx[5] < (3 * (1 << 13) + (1 << 11)))
501 : {
502 0 : sns_vq_idx[4] = 3; /*smaller fix_env "3" with 2 shiftbits and 9 remaining sign bits s1..s9 */
503 0 : sns_vq_idx[5] = sns_vq_idx[5] - (3 * (1 << 13));
504 0 : assert(sns_vq_idx[5] >= 0 && sns_vq_idx[5] < (1 << 11));
505 : }
506 : else
507 : { /* bit error */
508 0 : *bfi = plc_trigger_SNS2;
509 0 : if (*bfi != 0)
510 : {
511 0 : return;
512 : }
513 : }
514 0 : shape_idx = sns_vq_idx[4] + 2;
515 0 : sns_vq_idx[2] = shape_idx;
516 : } /* fixenv */
517 : }/*full*/
518 : }/*stage1B* + stage2 */
519 : } /*10+ bits*/
520 : }
521 : #endif
522 : #ifdef LRSNS_PC_SIGNAL_FIX
523 590506 : assert(*bfi == 0 || *bfi == 1 ); /* local SNS BFI-flag output check */
524 : #endif
525 : }
526 :
527 590506 : void processDecoderEntropy_fl(LC3_UINT8* bytes, LC3_INT numbytes, LC3_INT* mask_side, LC3_INT* bp_side, LC3_INT N, LC3_INT fs_idx,
528 : LC3_INT bw_cutoff_bits, LC3_INT* bfi, LC3_INT* gg_idx, LC3_INT* sns_vq_idx, LC3_INT* fac_ns_idx,
529 : LC3_INT* tns_numfilters, LC3_INT* tns_order, LC3_INT* ltpf_idx, LC3_INT* bw_cutoff_idx, LC3_INT* lastnz,
530 : LC3_INT* lsbMode, LC3PLUS_FrameDuration frame_dms
531 : #ifdef CR9_C_ADD_1p25MS
532 : , LC3_INT32 rx_status[2], LC3_INT16* mem_continuation
533 : #ifdef NEW_SIGNALLING_SCHEME_1p25
534 : , LC3_INT32 *ltpfinfo_frame_cntr /* set here , but also increased outside by bfi for the channel */
535 : #endif
536 : #endif
537 : )
538 : {
539 :
540 : #ifdef CR9_C_ADD_1p25MS_LRSNS
541 : LC3_INT32 plc_trigger_bw, plc_trigger_last_nz, plc_trigger_SNS1, plc_trigger_SNS2, bit,
542 : i, ltpf_tmp[3], bp_side_local, mask_side_local, rx_current_status, ltpf_idx_2_lrsns[3];
543 : LC3_UINT8 * ptr;
544 : #ifdef LRSNS_PC_SIGNAL_FIX
545 : LC3_INT bfiSNS;
546 : #endif
547 :
548 : //UNUSED(rx_status);
549 : //UNUSED(mem_continuation);
550 : UNUSED(rx_current_status);
551 : #else
552 : LC3_INT32 plc_trigger_bw, plc_trigger_last_nz, plc_trigger_SNS1, plc_trigger_SNS2, bit,
553 : i, ltpf_tmp[3], bp_side_local, mask_side_local, rx_current_status;
554 : LC3_UINT8 * ptr;
555 : UNUSED(rx_current_status);
556 : #endif
557 :
558 : #ifdef NEW_SIGNALLING_SCHEME_1p25
559 : UNUSED(rx_current_status);
560 : #endif
561 :
562 590506 : *bp_side = -1;
563 590506 : bp_side_local = numbytes - 1; /* Matlab offset by 1 */
564 590506 : mask_side_local = 1;
565 590506 : *mask_side = -1;
566 590506 : ptr = bytes;
567 590506 : *lsbMode = -1;
568 590506 : *lastnz = -1;
569 :
570 590506 : plc_trigger_bw = 1; /* Bandwidth */
571 590506 : plc_trigger_last_nz = 1; /* Last non-zero tuple */
572 :
573 590506 : plc_trigger_SNS1 = 1; /* SNS-VQ 2nd stage MPVQ data (24-25 bits) */
574 : #ifdef LRSNS_10MS_BFISIGNAL_FIX
575 590506 : plc_trigger_SNS2 = 1; /* SNS-VQ 2nd stage MPVQ data (10-16 bits) */
576 : #else
577 : plc_trigger_SNS2 = 2; /* SNS-VQ 2nd stage MPVQ data (10-16 bits) */
578 : #endif
579 : /* Bandwidth */
580 590506 : if (bw_cutoff_bits > 0) {
581 590506 : read_uint_fl(bw_cutoff_bits, ptr, &mask_side_local, &bp_side_local, bw_cutoff_idx);
582 :
583 590506 : if (fs_idx < *bw_cutoff_idx) {
584 0 : *bfi = plc_trigger_bw;
585 :
586 0 : if (*bfi) {
587 0 : return;
588 : }
589 : }
590 : } else {
591 0 : *bw_cutoff_idx = fs_idx;
592 : }
593 :
594 : /* Number of TNS filters */
595 : #ifdef CR9_C_ADD_1p25MS
596 590506 : if (frame_dms == LC3PLUS_FRAME_DURATION_1p25MS) {
597 0 : *tns_numfilters = 0;
598 : } else {
599 : #endif
600 590506 : if (*bw_cutoff_idx < 3 || frame_dms == LC3PLUS_FRAME_DURATION_2p5MS) {
601 2498 : *tns_numfilters = 1;
602 : } else {
603 588008 : *tns_numfilters = 2;
604 : }
605 : #ifdef CR9_C_ADD_1p25MS
606 : }
607 : #endif
608 :
609 : /* Last non-zero tuple */
610 590506 : read_uint_fl(getLastNzBits (N), ptr, &mask_side_local, &bp_side_local, lastnz);
611 590506 : *lastnz = (*lastnz + 1) * 2;
612 :
613 590506 : if (*lastnz > N) {
614 0 : *bfi = plc_trigger_last_nz;
615 0 : if (*bfi) {
616 0 : return;
617 : }
618 : }
619 :
620 : /* LSB mode bit */
621 590506 : read_bit_fl(ptr, &mask_side_local, &bp_side_local, lsbMode);
622 :
623 : /* Global gain */
624 590506 : read_uint_fl(8, ptr, &mask_side_local, &bp_side_local, gg_idx);
625 :
626 : /* TNS activation flag */
627 1769020 : for (i = 0; i < *tns_numfilters; i++) {
628 1178514 : read_bit_fl(ptr, &mask_side_local, &bp_side_local, &bit);
629 1178514 : tns_order[i] = bit;
630 : }
631 :
632 : /* LTPF activation flag */
633 : #ifdef NEW_SIGNALLING_SCHEME_1p25
634 590506 : ltpf_tmp[1] = 0; /* ltpf activation idx */
635 590506 : ltpf_tmp[2] = 0; /* quantized lag idx */
636 590506 : if (frame_dms != LC3PLUS_FRAME_DURATION_1p25MS)
637 : {
638 590506 : read_bit_fl(ptr, &mask_side_local, &bp_side_local, <pf_tmp[0]);
639 : }
640 : else
641 : { /* read one of {2, 6, 7} bits into ltp/ltpf/lag variable ltpf_idx[ 0 ... 2] */
642 0 : readLtpData_fl(ptr, bfi, &mask_side_local, &bp_side_local, ltpf_tmp, rx_status, ltpfinfo_frame_cntr, mem_continuation);
643 : } /* ! LC3PLUS_FRAME_DURATION_1p25MS */
644 : #else
645 : read_bit_fl(ptr, &mask_side_local, &bp_side_local, <pf_tmp[0]);
646 : #endif
647 :
648 : /* read SNS data */
649 : #ifdef CR9_C_ADD_1p25MS_LRSNS
650 590506 : ltpf_idx_2_lrsns[0] = ltpf_tmp[0]; /* raw LTP flag input to LRSNS */
651 590506 : ltpf_idx_2_lrsns[1] = ltpf_tmp[1]; /* raw LTPF flag input to LRSNS */
652 : #ifdef LRSNS_PC_SIGNAL_FIX
653 590506 : bfiSNS = 0; /* Local BFI flag for Errors SNS bit area */
654 590506 : readSNSData_fl(ptr, &bfiSNS, &mask_side_local, &bp_side_local, ltpf_idx_2_lrsns, sns_vq_idx, frame_dms, plc_trigger_SNS1, plc_trigger_SNS2);
655 590506 : if (bfiSNS != 0 )
656 : { /* corrupt SNSbits triggers PLC through global PLC flag.
657 : *bfi==2 and bfiSNS == 0 maintains bfi==2 for PC
658 : */
659 0 : *bfi = 1;
660 0 : return;
661 : }
662 :
663 590506 : if (frame_dms == LC3PLUS_FRAME_DURATION_1p25MS)
664 : { /* for 1.25ms and previously detected bit errors --> handle frame as a completely corrupt bad frame */
665 0 : if (*bfi == 2)
666 : {
667 0 : *bfi = 1;
668 0 : return;
669 : }
670 : }
671 :
672 : #else
673 : readSNSData_fl(ptr, bfi, &mask_side_local, &bp_side_local, ltpf_idx_2_lrsns, sns_vq_idx, frame_dms, plc_trigger_SNS1, plc_trigger_SNS2);
674 : if (*bfi != 0)
675 : {
676 : *bfi = 1;
677 : return;
678 : }
679 : #endif
680 : #else
681 : readSNSData_fl(ptr, bfi, &mask_side_local, &bp_side_local, sns_vq_idx, frame_dms, &plc_trigger_SNS1, &plc_trigger_SNS2);
682 : #endif
683 :
684 : /* LTPF data */
685 : #ifdef CR9_C_ADD_1p25MS
686 : #ifdef NEW_SIGNALLING_SCHEME_1p25
687 590506 : if ( frame_dms != LC3PLUS_FRAME_DURATION_1p25MS )
688 : {
689 590506 : ltpf_tmp[1] = 0;
690 590506 : ltpf_tmp[2] = 0;
691 590506 : if (ltpf_tmp[0] == 1)
692 : {
693 490741 : read_bit_fl(ptr, &mask_side_local, &bp_side_local, <pf_tmp[1]);
694 490741 : read_uint_fl(9, ptr, &mask_side_local, &bp_side_local, <pf_tmp[2]);
695 : }
696 : }
697 : #endif
698 : #endif
699 :
700 : #ifndef CR9_C_ADD_1p25MS
701 : if (ltpf_tmp[0] == 1)
702 : {
703 : read_bit_fl(ptr, &mask_side_local, &bp_side_local, <pf_tmp[1]);
704 : read_uint_fl(9, ptr, &mask_side_local, &bp_side_local, <pf_tmp[2]);
705 : }
706 : else
707 : {
708 : ltpf_tmp[1] = 0;
709 : ltpf_tmp[2] = 0;
710 : }
711 : #endif /* CR9_C_ADD_1p25MS */
712 :
713 2362024 : for (i = 0; i < 3; i++) {
714 1771518 : ltpf_idx[i] = ltpf_tmp[i];
715 : }
716 :
717 : /* Noise factor */
718 590506 : read_uint_fl(3, ptr, &mask_side_local, &bp_side_local, fac_ns_idx);
719 :
720 590506 : *bp_side = bp_side_local;
721 590506 : *mask_side = mask_side_local;
722 : }
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