Line data Source code
1 : /******************************************************************************
2 : * ETSI TS 103 634 V1.6.1 *
3 : * Low Complexity Communication Codec Plus (LC3plus) *
4 : * *
5 : * Copyright licence is solely granted through ETSI Intellectual Property *
6 : * Rights Policy, 3rd April 2019. No patent licence is granted by implication, *
7 : * estoppel or otherwise. *
8 : ******************************************************************************/
9 :
10 : #include "options.h"
11 : #include "wmc_auto.h"
12 : #include "functions.h"
13 :
14 : #ifdef CR9_C_ADD_1p25MS
15 :
16 : #ifdef NEW_SIGNALLING_SCHEME_1p25
17 : void writeLtpData_fl( LC3_UINT8* ptr, LC3_INT* bp_side, LC3_INT* mask_side, LC3_INT32* ltpf_idx, LC3_INT16* Tx_ltpf );
18 : #endif
19 :
20 : void writeSNSData_fl(LC3_UINT8* ptr, LC3_INT* bp_side, LC3_INT* mask_side, LC3PLUS_FrameDuration frame_dms, LC3_INT32* scf_idx);
21 : #else /* CR9_C_ADD_1p25MS */
22 : void writeSNSData_fl(LC3_UINT8* ptr, LC3_INT* bp_side, LC3_INT* mask_side, LC3_INT32* scf_idx);
23 : #endif /* CR9_C_ADD_1p25MS */
24 :
25 :
26 : static const LC3_INT32 gainMSBbits[4] = {1, 1, 2, 2};
27 : static const LC3_INT32 gainLSBbits[4] = {0, 1, 0, 1};
28 :
29 :
30 : #ifdef CR9_C_ADD_1p25MS
31 : #ifdef NEW_SIGNALLING_SCHEME_1p25
32 0 : void writeLtpData_fl(
33 : LC3_UINT8* ptr,
34 : LC3_INT* bp_side,
35 : LC3_INT* mask_side,
36 : LC3_INT32* ltpf_idx,
37 : LC3_INT16* Tx_ltpf
38 : )
39 : {
40 : LC3_INT32 tmp;
41 : LC3_INT32 bitsTx;
42 : /* Hdr, information , bits used
43 : 00 , no lag info , no phase info sum=2
44 : 010, PhaseA,LTPF=0, lagAbits=4 , sum=7 : pitch-PLC may be activated with old lag , 4 MSbs
45 : 011, PhaseB,LTPF=0, lagBbits=4*, sum=7* : pitch-PLC may be activated with fresh lag, 4* = reduced lag resolution in Quantized ltpf_idx domain for PLC
46 : 10 , PhaseA,LTPF=1, lagAbits=4 , sum=6 : LTPF may be activated with old lag
47 : 11 , PhaseB,LTPF=1, lagBbits=5 , sum=7 : LTPF activated with fresh lag
48 : */
49 :
50 :
51 0 : tmp = MIN(*Tx_ltpf, 1); /*phaseA==0, phaseB==1*/
52 :
53 0 : if (ltpf_idx[0] == 0)
54 : {
55 0 : write_bit_backward_fl(ptr, bp_side, mask_side, 0); /* "00" */
56 0 : write_bit_backward_fl(ptr, bp_side, mask_side, 0);
57 :
58 0 : *Tx_ltpf = 0;
59 : /* *Tx_ltpf A/B state forced to zero or kept at zero */
60 : /* decoder will discard any sofar in phase received phaseA MSB bits */
61 : }
62 0 : else if (ltpf_idx[1] == 0)
63 : {
64 : /* no current LTPF activation,
65 : lag transmitted for PLC, or for next frame LTPF activation */
66 0 : assert(ltpf_idx[0] != 0);
67 :
68 : /* A "010" 3 bits Hdr transmitted */
69 : /* B "011" 3 bits Hdr transmitted*/
70 :
71 0 : write_uint_backward_fl(ptr, bp_side, mask_side, 1, 2); /* "01"*/
72 0 : write_bit_backward_fl(ptr, bp_side, mask_side, tmp); /* phase A or phaseB */
73 :
74 0 : if (*Tx_ltpf == 0)
75 : { /* phase A transmission */
76 0 : assert(tmp == 0);
77 0 : assert((ltpf_idx[2] & ~(0x01ff)) == 0); /* only 9 bits info allowed within ltpf_idx[2] */
78 0 : tmp = (ltpf_idx[2] >> 5 ); /* shift_out LSBS, send 4 MSBs */
79 0 : *Tx_ltpf = (0x200 | ltpf_idx[2]); /* remember full lag, as phaseB sentinel in bit 10, */
80 : }
81 : else
82 : { /* phase B */
83 0 : assert(tmp == 1);
84 0 : assert(*Tx_ltpf > 511); /*sentinel in b10 should have been set in previous phaseA frame */
85 0 : tmp = ((*Tx_ltpf & 0x001f) >> 1); /* B send 4* LSBs, 1 bit truncated */
86 0 : *Tx_ltpf = 0; /* clear sentinel in b10 and the old remebered lag value */
87 : }
88 0 : write_uint_backward_fl(ptr, bp_side, mask_side, tmp, 4); /* 4 bits lag info Tx, when LTPF is deactivated */
89 : }
90 : else
91 : { /* LTPF activated */
92 : /* A "10" 2 bits Hdr */
93 : /* B "11" 2 bits Hdr */
94 0 : assert(ltpf_idx[0] != 0 && ltpf_idx[1] != 0);
95 :
96 0 : tmp |= 0x02;
97 0 : write_uint_backward_fl(ptr, bp_side, mask_side, tmp, 2);
98 :
99 0 : if (*Tx_ltpf == 0)
100 : {
101 0 : bitsTx = 4;
102 0 : assert((ltpf_idx[2] & ~(0x01ff)) == 0); /* only 9 bits info allowed within ltpf_idx[2] */
103 0 : tmp = (ltpf_idx[2] >> 5); /* shift away 5 LBS, LTPF active, send phaseA 4 MSBs */
104 :
105 0 : *Tx_ltpf = 0x0200 | ltpf_idx[2]; /* remember full lag in state *Tx_ltpf, add phaseB Tx state sentinel in bit 10 */
106 : }
107 : else
108 : {
109 0 : bitsTx = 5;
110 0 : tmp = (*Tx_ltpf & 0x001f); /* LTPF active B send 5 LSBs , full regular resolution */
111 0 : *Tx_ltpf = 0; /* clear sentinel in b10 and also the old remebered lag value */
112 : }
113 :
114 0 : write_uint_backward_fl(ptr, bp_side, mask_side, tmp, bitsTx); /* ltp==1 , ltpf==1, 4(A,MSBs) or 5(b, LSBs) bits */
115 : }
116 0 : }
117 : #endif /* NEW_SIGNALLING_SCHEME_1p25 */
118 590506 : void writeSNSData_fl(LC3_UINT8* ptr, LC3_INT* bp_side, LC3_INT* mask_side, LC3PLUS_FrameDuration frame_dms, LC3_INT32* scf_idx)
119 : #else
120 : void writeSNSData_fl(LC3_UINT8* ptr, LC3_INT* bp_side, LC3_INT* mask_side, LC3_INT32* scf_idx)
121 : #endif
122 : {
123 : #ifdef CR9_C_ADD_1p25MS_LRSNS
124 :
125 : LC3_INT32 submodeMSB, submodeLSB, tmp, gainMSB, gainLSB;
126 : LC3_INT16 write_legacy_sns_vq_bits;
127 : LC3_INT32 aux_idx;
128 : LC3_INT32 shape_idx;
129 : LC3_INT32 env_shape_idx;
130 : LC3_INT32 gain_idx;
131 : LC3_INT16 n5k;
132 :
133 : #else
134 : LC3_INT32 submodeMSB, submodeLSB, tmp, gainMSB, gainLSB;
135 : #endif
136 :
137 : #if defined(CR9_C_ADD_1p25MS) && !defined( CR9_C_ADD_1p25MS_LRSNS)
138 : UNUSED(frame_dms);
139 : #endif
140 :
141 : #ifdef CR9_C_ADD_1p25MS_LRSNS
142 590506 : write_legacy_sns_vq_bits = 1;
143 590506 : if (frame_dms == LC3PLUS_FRAME_DURATION_1p25MS) /* 9,10,29/30 */
144 : {
145 0 : write_legacy_sns_vq_bits = 0;
146 : }
147 590506 : if (write_legacy_sns_vq_bits != 0)
148 : {
149 : #endif
150 : /* SNS-VQ 1st stage */
151 590506 : write_uint_backward_fl(ptr, bp_side, mask_side, scf_idx[0], 5);
152 590506 : write_uint_backward_fl(ptr, bp_side, mask_side, scf_idx[1], 5);
153 :
154 : /* SNS-VQ 2nd stage side-info (3-4 bits) */
155 590506 : submodeMSB = scf_idx[2] / 2;
156 590506 : submodeLSB = scf_idx[2] & 1;
157 590506 : write_bit_backward_fl(ptr, bp_side, mask_side, submodeMSB);
158 590506 : gainMSB = scf_idx[3] >> (gainLSBbits[scf_idx[2]]);
159 590506 : gainLSB = scf_idx[3] & 1;
160 590506 : write_uint_backward_fl(ptr, bp_side, mask_side, gainMSB, gainMSBbits[scf_idx[2]]);
161 590506 : write_bit_backward_fl(ptr, bp_side, mask_side, scf_idx[4]);
162 :
163 : /* SNS-VQ 2nd stage MPVQ data (24-25 bits) */
164 590506 : if (submodeMSB == 0)
165 : {
166 285507 : if (submodeLSB == 0)
167 : {
168 269685 : tmp = scf_idx[6] + 2;
169 : }
170 : else
171 : {
172 15822 : tmp = gainLSB;
173 : }
174 :
175 285507 : tmp = tmp * 2390004 + scf_idx[5];
176 285507 : write_uint_backward_fl(ptr, bp_side, mask_side, tmp, 25);
177 : }
178 : else
179 : {
180 304999 : tmp = scf_idx[5];
181 :
182 304999 : if (submodeLSB != 0)
183 : {
184 11275 : tmp = 2 * tmp + gainLSB + 15158272;
185 : }
186 304999 : write_uint_backward_fl(ptr, bp_side, mask_side, tmp, 24);
187 : }
188 : #ifdef CR9_C_ADD_1p25MS_LRSNS
189 : }
190 590506 : if (write_legacy_sns_vq_bits == 0)
191 : {
192 : /* SNS-VQ 1st stage is jointly multiplexed into 9 bits or 10 bits */
193 : /* input scf_idx[0], has the stage1 index for one of BCA or B* */
194 0 : aux_idx = scf_idx[1]; /* aux value: we have the LS, or the s0 sign bit */
195 0 : shape_idx = scf_idx[2]; /* st2 shape 0 .. 5 , where [2.3.4.5] are fixed FESS shapes */
196 0 : gain_idx = scf_idx[3]; /* idx of 2-3 bits valued gains */
197 :
198 0 : if (shape_idx == 0 && scf_idx[0] >= 0)
199 : { /*aux==2 --> split mode st1B (aux==2), + a 2 bit gain + P(5,6)10.96b + P(8,2)7b */
200 0 : assert(shape_idx == 0 && gain_idx < 4);
201 : }
202 0 : if ((shape_idx == 1) && scf_idx[0] >= 0)
203 : { /* regular mode st1B , + a 3 bit gain + P(15,5) */
204 0 : assert(shape_idx == 1 && gain_idx >= 0 && gain_idx < 8);
205 : }
206 0 : if ((shape_idx >= 2) && scf_idx[0] >= 0)
207 : { /* regular mode st1B , + a 3 bit gain + fixenv */
208 0 : assert(shape_idx >= 2 && shape_idx <= 5 && gain_idx >= 0 && gain_idx < 8);
209 : }
210 :
211 : /* b0-b8 b9
212 : segm , idx9b , stop bit, comment use
213 : -----+--------+---------
214 : A | 510,511| n/a, 2 entries, 9 bit total
215 : ------+--------+--------
216 : B | 0--169 | 1 , 170 entries, 10 bit total
217 : ------+--------+--------
218 : C | 170-339| 1 , 170 entries, 10 bit total
219 : ------+--------+--------+------------
220 : */
221 :
222 0 : if (scf_idx[0] >= 510)
223 : { /* stage1A */
224 0 : assert(scf_idx[0] < (1 << 9));
225 0 : write_uint_backward_fl(ptr, bp_side, mask_side, scf_idx[0], 9); /* currently writes 510 or 511 */
226 0 : shape_idx = -9; /* only crude stage 1 A , no more bits to send */
227 : }
228 0 : else if ( (scf_idx[0] < 2 * 170) && (shape_idx < 0) )
229 : {
230 0 : if (scf_idx[0] < 170)
231 : {
232 0 : write_uint_backward_fl(ptr, bp_side, mask_side, scf_idx[0] + 0 * 170, 9); /* 1B */
233 : }
234 0 : else if (scf_idx[0] < 2 * 170)
235 : {
236 0 : write_uint_backward_fl(ptr, bp_side, mask_side, (scf_idx[0] - 170) + 1 * 170, 9); /* 1C */
237 : }
238 : /* write the stop bit value sentinel value "1", so that the demux dec_entropy can stop already at (9+1)=10 bits */
239 :
240 0 : write_uint_backward_fl(ptr, bp_side, mask_side, 1, 1); /* dec_entropy will read a 1 "stop" bit */
241 :
242 : /* pitch_rx and ltpf_rx handled separately */
243 : }
244 0 : else if (shape_idx == 0)
245 : {
246 : /* aux info as a part of (9+1) 10 initial bits */
247 : /* b0-b8 b9
248 : segm , idx9b , stop bit, comment use
249 : -----+--------+---------
250 : B* | 0--169 | 0 , --> aux=0, 170, 2b+17b for stage2 'LR_SplitLF', 29 bit total
251 : ------+--------+--------+-------
252 : B* | 170-339| 0 , --> aux=1, 170, 2b+17b for stage2 'LR_SplitLF', 29 bit total
253 : ------+--------+--------+-------
254 : */
255 : /* 29 bit total LR_splitLF */
256 0 : assert(scf_idx[0] >= 0 && scf_idx[0] < 170); /* st1B range */
257 0 : assert(aux_idx >= 0 && aux_idx <= 1); /* aux_bit can only be 1 or 0 */
258 0 : write_uint_backward_fl(ptr, bp_side, mask_side, scf_idx[0] + aux_idx * 170, 9); /* aux_bit defined by region 0..339 region in decoder */
259 0 : write_uint_backward_fl(ptr, bp_side, mask_side, 0, 1); /* "stop" bit. always zero for 'LR_splitLF' */
260 :
261 0 : write_uint_backward_fl(ptr, bp_side, mask_side, gain_idx, 2); /* always 2bits == 4 gain levels for the splitLF mode */
262 :
263 0 : n5k = 6;
264 0 : if (scf_idx[5] < 0) {
265 0 : assert(scf_idx[5] == -8 );
266 0 : n5k = 8;
267 : }
268 :
269 0 : if (n5k == 6)
270 : { /* multiplex remaining 10 + 1+6 bit */
271 0 : write_uint_backward_fl(ptr, bp_side, mask_side, scf_idx[4], 10); /* 29b P(5,6)=10.94 in LS+10 bits, */
272 0 : write_uint_backward_fl(ptr, bp_side, mask_side, scf_idx[5] & 0x1, 1); /* LS for P(8,2)=7 */
273 0 : write_uint_backward_fl(ptr, bp_side, mask_side, scf_idx[5] >> 1, 6); /* mPVQ(8,2) in 6 */
274 : }
275 : else
276 : { /* LF is PVQ(N=5,K=8), HF is all zero , multiplexed as top section in stage2 10b , + 7b */
277 : /* scf_idx[4] is in the range [0 ... (SNSLR_NPVQ_L5K8 >>1)[, [0 .. 2945[ , 11.52 bits */
278 : /* 985 - 1024 = 39 entries where we now use only 32 (5 bits) */
279 : /* index_to_send = (SNSLR_NPVQ_L5K6 >> 1) + (scf_idx[4] & 0x001f) , range [985 .. 1017[ , i.e. 7 values are not sent:[1018 ... 1023] */
280 0 : write_uint_backward_fl(ptr, bp_side, mask_side, (SNSLR_NPVQ_L5K6 >> 1) + (scf_idx[4] & 0x001f), 10); /* 5 lsb's as top in the 10b */
281 0 : assert((scf_idx[4] >> 5) < (1 << 7));
282 0 : write_uint_backward_fl(ptr, bp_side, mask_side, scf_idx[4] >> 5, 7); /* 7 msb's of mpvq(5,8)*/
283 : }
284 : }
285 0 : else if (shape_idx == 1)
286 : {
287 : /* b0-b8 b9
288 : segm , idx9b , stop bit, comment use
289 : ------+--------+--------+------------
290 : B* | 340-509| 1 --> aux=1, 170, 3b+17b for stage2 'LR_full', 30 bit total
291 : ------+--------+--------+-------
292 : B* | 340-509| 0 --> aux=0, 170, 3b+17b for stage2 'LR_full', 30 bit total
293 : ------+--------+--------+-------
294 : */
295 0 : assert(scf_idx[0] >= 0 && scf_idx[0] < 170); /* st1B* range */
296 :
297 0 : write_uint_backward_fl(ptr, bp_side, mask_side, scf_idx[0] + 2 * 170, 9); /* stage1B* signal */
298 0 : write_uint_backward_fl(ptr, bp_side, mask_side, aux_idx, 1); /* auxbit transmitted in the stop bit location */
299 :
300 0 : write_uint_backward_fl(ptr, bp_side, mask_side, gain_idx, 3); /*30b always 8 gain levels in 3 bits for the full mode */
301 : /* the next 17 bit index is used to decode submode 1==full or one of submode 2,3,4,5 == fix */
302 0 : assert(scf_idx[4] >= 0 && scf_idx[4] < ((SNSLR_NPVQ_L15K5 >> 1)));
303 0 : write_uint_backward_fl(ptr, bp_side, mask_side, scf_idx[4], 17); /* P(15,5) without the leading sign, 16.6593 bits, written */
304 : }
305 : else
306 : { /* Fixed shapes 2(ones, env0) and 3(env1) , 4(env2), and later 5(env3) */
307 0 : assert(shape_idx >= 2 && shape_idx <= 5);
308 : /* env 0,1,2, : s0(in aux) + shift(2bits)+ 11 signs , section size 8192
309 : env 3 : s0(in aux) + shift(2bits)+ 9 signs , section size 2048
310 : */
311 0 : env_shape_idx = scf_idx[4];
312 0 : assert(env_shape_idx == (shape_idx - 2)); /*scf_idx[4] has the fixed env index*/
313 :
314 0 : assert(scf_idx[0] >= 0 && scf_idx[0] < 170); /* st1B* range */
315 :
316 0 : write_uint_backward_fl(ptr, bp_side, mask_side, scf_idx[0] + 2 * 170, 9); /* stage1B* signal */
317 0 : write_uint_backward_fl(ptr, bp_side, mask_side, aux_idx, 1); /* auxbit transmitted in the stop bit location */
318 :
319 0 : write_uint_backward_fl(ptr, bp_side, mask_side, gain_idx, 3); /* for 30bit its is always 3 gain bits */
320 :
321 0 : if (shape_idx < 5) /*2,3,4*/
322 : {
323 0 : assert(scf_idx[5] >= 0 && scf_idx[5] < (1 << 13));
324 0 : assert((SNSLR_NPVQ_L15K5 >> 1) + env_shape_idx * (1 << 13) + scf_idx[5] < (1 << 17));
325 : /* offset is PVQ(15,5) without leading sign */
326 : /* int32_t tmp_idx = (SNSLR_NPVQ_L15K5 >> 1) + env_shape_idx * (1 << 13) + scf_idx[5]; */
327 0 : write_uint_backward_fl(ptr, bp_side, mask_side, (SNSLR_NPVQ_L15K5 >> 1) + env_shape_idx * (1 << 13) + scf_idx[5], 17);
328 : }
329 : else
330 : {
331 0 : assert(shape_idx == 5);
332 0 : assert(env_shape_idx == 3);
333 0 : assert(scf_idx[5] < (1 << 11));
334 0 : assert(((SNSLR_NPVQ_L15K5 >> 1) + 3 * (1 << 13) + scf_idx[5]) < (1 << 17));
335 : /* offset is (15,5) without leading sign */
336 0 : write_uint_backward_fl(ptr, bp_side, mask_side, (SNSLR_NPVQ_L15K5 >> 1) + 3 * (1 << 13) + scf_idx[5], 17);
337 : }
338 : }
339 : }
340 : #endif
341 590506 : }
342 :
343 590506 : void processEncoderEntropy_fl(LC3_UINT8* bytes, LC3_INT* bp_side, LC3_INT* mask_side, LC3_INT numbytes, LC3_INT bw_cutoff_bits,
344 : LC3_INT bw_cutoff_idx, LC3_INT lastnz, LC3_INT N, LC3_INT lsbMode, LC3_INT gg_idx, LC3_INT num_tns_filters,
345 : LC3_INT* tns_order, LC3_INT* ltpf_idx, LC3_INT* scf_idx, LC3_INT fac_ns_idx,
346 : LC3_INT bfi_ext, LC3_INT fs_idx
347 : #ifdef CR9_C_ADD_1p25MS
348 : , LC3PLUS_FrameDuration frame_dms, LC3_INT16* Tx_ltpf
349 : #endif
350 : )
351 : {
352 : LC3_UINT8* ptr;
353 : LC3_INT i;
354 :
355 590506 : LC3_INT16 lastnzTrigger[5] = {63, 127, 127, 255, 255};
356 :
357 : #if defined(CR9_C_ADD_1p25MS) && !defined(CR9_C_ADD_1p25MS_LRSNS)
358 : UNUSED(Tx_ltpf);
359 : #endif
360 590506 : *bp_side = numbytes - 1;
361 590506 : *mask_side = 1;
362 590506 : ptr = bytes;
363 :
364 : /* Bandwidth */
365 590506 : if (bw_cutoff_bits > 0) {
366 590506 : write_uint_backward_fl(ptr, bp_side, mask_side, bw_cutoff_idx, bw_cutoff_bits);
367 : }
368 :
369 : /* Last non zero touple */
370 590506 : if (bfi_ext == 1) {
371 0 : write_uint_backward_fl(ptr, bp_side, mask_side, lastnzTrigger[fs_idx], getLastNzBits (N));
372 : }
373 : else
374 : {
375 590506 : write_uint_backward_fl(ptr, bp_side, mask_side, lastnz / 2 - 1, getLastNzBits (N));
376 : }
377 :
378 : /* LSB mode bit */
379 590506 : write_bit_backward_fl(ptr, bp_side, mask_side, lsbMode);
380 :
381 : /* Global gain */
382 590506 : write_uint_backward_fl(ptr, bp_side, mask_side, gg_idx, 8);
383 :
384 : /* TNS activation flag */
385 1769020 : for (i = 0; i < num_tns_filters; i++) {
386 1178514 : write_bit_backward_fl(ptr, bp_side, mask_side, MIN(1, tns_order[i]));
387 : }
388 :
389 : /* LTPF activation flag */
390 : #ifdef CR9_C_ADD_1p25MS
391 : #ifdef NEW_SIGNALLING_SCHEME_1p25
392 590506 : if (frame_dms == LC3PLUS_FRAME_DURATION_1p25MS)
393 : {
394 0 : writeLtpData_fl(ptr, bp_side, mask_side, ltpf_idx, Tx_ltpf); /* LTP and LTPF-active and interleaved lag-idx */
395 : }
396 : else
397 : {
398 590506 : write_bit_backward_fl(ptr, bp_side, mask_side, ltpf_idx[0]); /* ltp tx bit */
399 : }
400 : #endif
401 : #else
402 : write_bit_backward_fl(ptr, bp_side, mask_side, ltpf_idx[0]);
403 : #endif /* CR9_C_ADD_1p25MS */
404 :
405 : /* SNS data*/
406 : #ifdef CR9_C_ADD_1p25MS
407 590506 : writeSNSData_fl(ptr, bp_side, mask_side, frame_dms, scf_idx);
408 : #else
409 : writeSNSData_fl(ptr, bp_side, mask_side, scf_idx);
410 : #endif
411 :
412 : /* LTPF data */
413 : #ifdef CR9_C_ADD_1p25MS
414 : #ifdef NEW_SIGNALLING_SCHEME_1p25
415 590506 : if ((frame_dms != LC3PLUS_FRAME_DURATION_1p25MS ) && (ltpf_idx[0] == 1) )
416 : {
417 490741 : write_uint_backward_fl( ptr, bp_side, mask_side, ltpf_idx[1], 1 );
418 490741 : write_uint_backward_fl( ptr, bp_side, mask_side, ltpf_idx[2], 9 );
419 : }
420 : #endif
421 : #else /* CR9_C_ADD_1p25MS */
422 : if (ltpf_idx[0] == 1) {
423 : write_uint_backward_fl(ptr, bp_side, mask_side, ltpf_idx[1], 1);
424 : write_uint_backward_fl(ptr, bp_side, mask_side, ltpf_idx[2], 9);
425 : }
426 : #endif /* CR9_C_ADD_1p25MS */
427 :
428 : /* Noise factor */
429 590506 : write_uint_backward_fl(ptr, bp_side, mask_side, fac_ns_idx, 3);
430 590506 : }
431 :
432 5705530 : void write_uint_backward_fl(LC3_UINT8* ptr, LC3_INT* bp_side, LC3_INT* mask_side, LC3_INT val, LC3_INT numbits)
433 : {
434 : LC3_INT k, bit;
435 :
436 44303974 : for (k = 0; k < numbits; k++) {
437 38598444 : bit = val & 1;
438 38598444 : write_bit_backward_fl(ptr, bp_side, mask_side, bit);
439 38598444 : val = val >> 1;
440 : }
441 5705530 : }
442 :
443 372431196 : void write_bit_backward_fl(LC3_UINT8* ptr, LC3_INT* bp_side, LC3_INT* mask_side, LC3_INT bit)
444 : {
445 372431196 : if (bit != 0) {
446 179064981 : ptr[*bp_side] = ptr[*bp_side] | *mask_side;
447 : }
448 :
449 372431196 : if (*mask_side == 128) {
450 46295590 : *mask_side = 1;
451 46295590 : *bp_side = *bp_side - 1;
452 : } else {
453 326135606 : *mask_side = *mask_side << 1;
454 : }
455 372431196 : }
|
